
Design Verification Engineer, Multimedia, Silicon
職缺摘要
技術需求
學歷要求
Bachelor
職缺描述
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Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
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Create and enhance constrained-random verification environments using System Verilog and UVM.
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Identify and write all types of coverage measures for stimulus and corner-cases.
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Debug tests with design engineers to deliver functionally correct design blocks.
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Close coverage measures to identify verification holes and to show progress towards tape-out.
Minimum qualifications:
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
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1 year of experience with verification methodologies and languages such as UVM or SystemVerilog.
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Experience with object oriented programming.
Preferred qualifications:
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Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
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Experience creating and using verification components and environments in a standard verification methodology such as UVM.
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Experience with image processing or other multimedia IPs such as Display or Video Codec.
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Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture.
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Experience with verification techniques, System Verilog Assertions (SVA), and assertion-based verification.
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Experience with low-power DV, and support of SOC DV or gate-level simulation(GLS).