Silicon Physical Design CAD Engineer

• Co-work with project team for a more efficient and effective flow execution and results review mechanism in PDV field.

• Co-work with the methodology team to define Physical Design Verification (PDV) flow requirements for technology nodes Design Rule Check (DRC), Layout Versus Schematic (LVS), and Programmable Electrical Rule Check (PERC) checks.

• Import new features, improve job efficiency, and maintain a stable flow in PDV analysis to meet technology and project needs.

• Provide flow usage and execution support with documentation, training and troubleshooting.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a similar field, or equivalent practical experience.

• 4 years of experience in scripting languages such as Perl, TCL, Shell, or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a similar field.

• 5 years of experience with physical design, signoff, or CAD.

• Experience with setting advanced technology nodes flows.

• Experience in extraction of design parameters, Quality of Results (QoR) metrics, analyzing trends, and creating dashboards/reports.

• Experience in Electronic Design Automation (EDA) vendor management in feature evaluation and issue support.

• Familiarity with Siemens/Calibre or Synopsys/IC Validator.