
Post Silicon Advanced Packaging Engineer
職缺摘要
技術需求
學歷要求
Bachelor
職缺描述
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Monitor, analyze, and improve package-level yields for 2.5D/3D architectures. Track yield from known good die and interposer testing through final assembly and Class/System-Level Test.
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Identify and root-cause major yield detractors. Use statistical tools to correlate final package failures back to wafer-level testing, substrate defects, or assembly process variations.
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Act as the primary technical interface with foundries and OSATs. Drive suppliers on process control monitors, recipe optimizations, and corrective actions for assembly-induced defects.
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Characterize complex, multi-chip module failure mechanisms. Coordinate destructive and non-destructive Failure Analysis (FA) techniques.
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Feed post-silicon yield and FA learning back to the Design for Manufacturing and Design for Test teams to improve next-generation Chip-on-Wafer-on-Substrate (CoWoS)/Embedded Multi-die Interconnect Bridge (EMIB) product architectures.
Minimum qualifications:
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
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8 years of experience with product engineering and test engineering.
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Experience with 2.5D/3D packaging technologies, interposers, high-density substrates, and micro-bump metallurgical bonding.
Preferred qualifications:
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Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
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Experience evaluating customer returns, identifying assembly issues and improvement plans.
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Experience in Python/Perl for data automation, statistical analysis, and yield management systems.
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Understanding of high bandwidth memory integration, die-to-die interfaces, and high-speed signal integrity challenges within a package.