Post Silicon Advanced Packaging Engineer

• Monitor, analyze, and improve package-level yields for 2.5D/3D architectures. Track yield from known good die and interposer testing through final assembly and Class/System-Level Test.

• Identify and root-cause major yield detractors. Use statistical tools to correlate final package failures back to wafer-level testing, substrate defects, or assembly process variations.

• Act as the primary technical interface with foundries and OSATs. Drive suppliers on process control monitors, recipe optimizations, and corrective actions for assembly-induced defects.

• Characterize complex, multi-chip module failure mechanisms. Coordinate destructive and non-destructive Failure Analysis (FA) techniques.

• Feed post-silicon yield and FA learning back to the Design for Manufacturing and Design for Test teams to improve next-generation Chip-on-Wafer-on-Substrate (CoWoS)/Embedded Multi-die Interconnect Bridge (EMIB) product architectures.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 8 years of experience with product engineering and test engineering.

• Experience with 2.5D/3D packaging technologies, interposers, high-density substrates, and micro-bump metallurgical bonding.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• Experience evaluating customer returns, identifying assembly issues and improvement plans.

• Experience in Python/Perl for data automation, statistical analysis, and yield management systems.

• Understanding of high bandwidth memory integration, die-to-die interfaces, and high-speed signal integrity challenges within a package.