Silicon Test Engineering Manager

• Design, implement, and manage Integrated Circuit (IC) product bring-up, verification, and characterization programs for NPI, including ATE test programs, load boards, and probe cards using ATE platforms such as UFLEX or 93K.

• Collaborate with vendors and internal teams to engineer high-volume ATE manufacturing solutions tailored for advanced packaging.

• Execute product and Defective parts per million (DPPM) correlation between ATE and system-level environments for new products.

• Enhance test coverage and resolve various failure modes via troubleshooting on ATE and System Level Testing (SLT) systems.

• Direct production sustaining activities, including program upgrades, yield optimization, test time reduction, lot disposition, and Return Merchandise Authorization (RMA) analysis.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, related degree or equivalent practical experience.

• 10 years of experience in the semiconductor industry.

• 5 years of experience managing IC qualification, production releases, and system-level testing, with a focus on data review, yield enhancement, and test time.

• Experience with integrated circuit (IC) testing, and in Yield and Bin Pareto analysis.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, or related degree.

• Experience in semiconductor processing, VLSI product or test engineering, with SLT, and using the advantest platform.

• Experience with ATE platforms (Teradyne UltraFlex SoC and Advantest 93K), with knowledge of high-speed interfaces (DDR, PCIe, SERDES).

• Understanding of design for testing (DFT) methodologies, including memory BIST, JTAG, Scan/ATPG, and testing for PVT and temperature sensors.

• Understanding of advanced packaging technologies such as InFO and 2.5D.

• Ability to utilize data analysis tools (O+, Datapower, or JMP).