NVIDIA
Senior Physical Design Engineer
其他地區正職5+年硬體工程發布：2026-05-13
職缺摘要
•職責：負責 STA 與設計約束、時序違規除錯與 ECO 實現、高性能晶片分割的 Floor Planning 與 P&R 工作；電源網格規劃、時序閉合、多模式多角點分析與物理驗證
•領域：高性能低功耗 SoC 設計實現、NVLINK 晶片設計、5nm/7nm/3nm 先進製程 VLSI 物理設計
•技能：RTL2GDS、STA、Floor Planning、Place and Route、Power Grid Planning、Clock Tree Synthesis、RC Extraction、Cross talk Analysis、IR Drop Analysis、EM Analysis、ERC、DRC、LVS、Synopsys ICC2、Synopsys DC、Synopsys PT、Synopsys STAR、Synopsys ICV、Cadence Genus、Cadence Innovus、Cadence Tempus、Python、Perl、Tcl、Make
•亮點：資深實體設計職位，參與 NVIDIA NVLINK 晶片設計，涵蓋從消費電子到自駕車與 AI 應用的產品線
技術需求
RTL2GDSSTAFloor PlanningPlace and RoutePower Grid PlanningClock Tree SynthesisRC ExtractionIR Drop AnalysisEM AnalysisERC
學歷要求
Master
職缺描述
We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power SOC’s.
What you'll be doing:
- Responsible on STA / design constraint for advanced technology nodes.
- Debugging timing violations and rolling in functional, Timing ECO’s and netlist formal verification.
- Responsible to Floor Planning and Place and route (P&R) of High-performance chip partitions.
- Work on power grid planning, Clock tree Synthesis (CTS) and timing closure.
- Multi mode and multi corner timing closure, RC extraction, Cross talk, IR drop and EM analysis.
- Physical verification including ERC, DRC, LVS etc.
What we need to see:
- BSEE / MSEE or equivalent experience.
- Minimum 5+ years of experience in VLSI physical design implementation on 16nm, 7nm, 5nm or 3nm technology.
- Able to assist in design flow development and debugging.
- Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
- To be successful you should possess strong analytical and debugging skills.
- Proficiency using Python, Perl, Tcl, Make scripting is desired.