USB IP Verification Engineer
職缺摘要
學歷要求
Master
職缺描述
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
THE ROLE:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
THE PERSON:
The candidate is expected to exhibit strong verbal and written communication skills in both Chinese and English; specialized knowledge; broad technical knowledge that facilitates integrative thinking and drives the execution of high-quality, timely results; the capability to solve complex, novel, and non-recurring problems; and the ability to make critical decisions in technical areas.
KEY RESPONSIBILITIES:
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Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge
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Provide the technical leadership to the DV team for the new Southbridge project
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Work independently on various DV tasks and provide technical guidance to the DV team.
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Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
PREFERRED EXPERIENCE:
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Master's in Electrical Engineering, Computer Science, or related
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Good understanding of ASIC design verification flow
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RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
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Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc.
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USB experience is a plus
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Experience in AI debug/analysis is preferred
ACADEMIC CREDENTIALS:
MSEE or BSEE with solid experiences in digital ASIC/SOC design verification.
MS/BS degree in EE or CS with experience in digital IP/SOC design verification.
LOCATION:
Hsinchu/Taipei
_Benefits offered are described:_AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
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This posting is for an existing vacancy.