Ambarella
VLSI Design Verification Engineer_2
新竹正職不限IC 設計發布：2026-07-16
職缺摘要
職責開發複雜SoC/IP驗證計畫；建立測試平台、斷言與覆蓋率模型；與架構師、設計師及晶片後端團隊協作
領域AI邊緣運算視覺處理器，VLSI驗證
技能SystemVerilog、UVM、Verilog、C、C++、Perl、Python、覆蓋率導向驗證、斷言式驗證
亮點採用AI輔助工具加速驗證流程，參與下一代SoC設計
學歷要求
Bachelor
職缺描述
AI Vision Processors For Edge Applications:
Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.:
Job Description
We are looking for talented engineers to join our VLSI Verification team. You’ll work on next-generation SoCs, applying advanced verification methodologies (SystemVerilog/UVM, coverage-driven, assertion-based) and leveraging AI-assisted tools to accelerate testplan writing, assertion development, and debug.
Responsibilities
- Develop and execute verification plans for complex SoCs/IPs
- Build testbenches, assertions, and coverage models
- Collaborate with architects, designers, and post-silicon teams
- Ensure correctness and reliability of cutting-edge designs
Why Join Us
- Cutting-edge verification with AI-powered flows
- Work alongside global world-class engineers
- Accelerated growth in a learning-driven culture If you are smart, curious, and eager to learn, join us and shape the future of silicon innovation!
Qualifications
- Bachelor’s, Master’s, or PhD in EE/CS or related field
- Strong background in digital design and computer architecture
- Experience with SystemVerilog/UVM/Verilog/C/C++ (script with Perl/Python is a plus)
- Strong debugging, analytical, and problem-solving skills