Monolithic Power Systems

Sr. Digital Verification Engineer (Taipei)

台北正職5+年軟體工程發布：2026-04-23

職缺摘要

•職責：數位及混訊號 IC 驗證計畫制定、UVM 與 SystemVerilog 驗證環境建置、測試案例與檢查器開發、測試結果分析除錯及涵蓋率分析

•領域：ASIC 數位驗證、混訊號 IC、電源管理 IC（switching regulators、power management ICs）

•技能：SystemVerilog、UVM、數位模擬器、覆蓋率分析工具、形式驗證工具、Gate-level 驗證、RTL/行為模型編碼、TCL、Python、C/C++、I2C、I3C、SPI、USB、PMBUS

•亮點：MPS 資深驗證工程師職缺，著重電源管理及混訊號 IC 驗證，需 5-8 年 ASIC 數位驗證經驗

技術需求

SystemVerilogUVMASICDigital SimulationCode CoverageFunctional Coverage

職缺描述

Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery architectures. At MPS, we cultivate creativity, are passionate about sustainability, and are committed to providing leading-edge products and innovation to our customers. Our portfolio of technology helps power our world ---come join our team and see how YOU can make a difference.

Job Description:

A Senior Digital Verification Engineer assists in the verification of digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions.

MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.

Essential Functions:

Generation of verification plans based on design requirements and product datasheets of digital / mixed- signal IC’s.
Close interaction Digital designers and Analog Designers to develop System Level and Behavioral Models.
Create Digital Verification Environment with UVM and System Verilog.
Write Digital and Mixed-Signal testcases and assertions/checkers.
Analyze and debug test results, code coverage and functional coverage.
Document and support detailed test plans and reviews.
Develop Verification IPs and standard tests, environments, checkers, etc.
Automation and scripting.
Gate-Level verification.
Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, Coverage analysis tools, and formal verification tools.
Good written/verbal communication skills and strong team work/collaboration.

Qualifications:

MS in Electrical Engineering with 5-8 years of experience in verification of digital ASIC design.
Has the ability to follow instructions/tasks according to design specifications/procedures.
Strong knowledge of ASIC development process and digital design techniques.
Strong knowledge of standard DV languages (SystemVerilog, UVM) and in behavioral/RTL coding.
Executing tasks that hit project milestone.
Knowledge/Experience with the following is a plus:Embedded designs and/or firmware development
Knowledge of power management industry/applications
I2C, I3C, SPI, USB, PMBUS
Scripting and automation languages like TCL, Python and C/C++

Monolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status.

Sr. Digital Verification Engineer (Taipei)

職缺摘要

技術需求

學歷要求

職缺描述