Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
We are seeking a highly experienced Engineer in 3DIC Yield Analytics to lead advanced diagnostics and drive data-driven yield learning for next-generation 2.5D and 3DIC technologies. This role focuses on extracting actionable insights from large-scale semiconductor data using advanced yield analytics and diagnostics methodologies. The candidate will work across wafer, die, and multi-die stack levels to identify yield limiters and enable rapid root-cause resolution.
Key Responsibilities:
·Lead 3DIC yield analytics initiatives to drive systematic yield improvement across wafer, packaging, and test operations
·Perform deep analysis of large-scale diagnostics datasets to identify systematic, random, and parametric failure mechanisms
·Develop and scale methodologies for analyzing heterogeneous 3DIC data (wafer sort, final test, module, and stack-level data)
·Conduct advanced scan diagnostics and ATPG analysis, including clustering and root-cause decomposition
·Analyze TSV, interposer, and 3D stack-related failures to identify cross-layer interactions and integration challenges
·Drive structured root cause analysis (RCA) and validate failure mechanisms
·Interpret memory diagnostics data, including bitmap analysis across SRAM and DRAM (stacked DRAM)
·Correlate diagnostic findings with process, design, and packaging factors to enable yield learning
Qualifications:
·Bachelor’s degree in Engineering or related field with 6+ years of experience, OR Master’s degree with 5+ years, OR Ph.D. with 4+ years
·Strong experience in yield analytics, diagnostics, and semiconductor data analysis
·Proven track record of driving yield improvement in high-volume manufacturing
Preferred Qualifications:
·Deep understanding of 3DIC architectures, TSV/interposer technologies, and advanced packaging flows
·Experience building and scaling yield analytics frameworks and methodologies
·Familiarity with layout/process correlation and defect modeling
·Hands-on experience applying ML/AI techniques in yield analytics or diagnostics
·Strong communication skills and demonstrated technical leadership
·Experience in DRAM diagnostics is a plus
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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