We Are:
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are:
You have spent over a decade deep in physical design, and you know the difference between a floorplan that looks good in a review and one that actually closes timing at 5nm. The thrill for you is solving the puzzle of how a DDR PHY fits into a customer's SoC when their bump map is locked and their power budget is impossible. You have been the person who sketches a solution on a whiteboard, explains the tradeoffs to a skeptical customer engineer, and then briefs your implementation team on what needs to happen next.
You are comfortable being the technical anchor. When a customer asks if their HBM subsystem can work in a multi-die package with UCIe, you think through signal integrity, DFT implications, and foundry constraints, and you come back with a real answer. You have managed teams or led complex blocks, so you know how to keep engineers moving without micromanaging. At Synopsys, you will work on the hardest memory and interconnect IP problems in the industry.
What You'll Be Doing:
- Oversee physical design implementation of DDR, HBM, and UCIe PHYs from floorplan through tapeout in FinFET nodes at 7nm and below
- Analyze customer requirements and propose technical solutions covering floorplan, bump mapping, DFT strategy, packaging, and process technology
- Serve as primary technical interface with customers and internal R&D, translating constraints into executable design plans
- Enforce Synopsys Quality Management System, writing project documentation, running design reviews, and certifying delivery checklists
- Work hands-on with Synopsys EDA tools including ICC2, Fusion Compiler, PrimeTime, and StarRC to guide implementation and troubleshoot critical issues
- Feed implementation learnings back into IP R&D to improve product roadmaps and design methodologies
- Develop technical presentations for customers and sales teams, and contribute to marketing collateral
The Impact You Will Have:
- Enable tier-one semiconductor companies to integrate cutting-edge memory and die-to-die IP into their most advanced SoCs
- Reduce project risk by catching floorplan, DFT, or packaging issues early, before they become costly late-stage problems
- Improve Synopsys IP quality by channeling field implementation experience into product development priorities
- Build customer confidence and long-term partnerships by being the technical voice they trust when projects get hard
- Mentor implementation engineers, raising the technical bar and ensuring consistent delivery quality
- Shape how Synopsys positions DDR, HBM, and UCIe solutions by grounding marketing in real project outcomes
What You'll Need:
- BS or MS in Electrical Engineering, Computer Engineering, or related field
- 10+ years of hands-on ASIC or SoC physical design experience at top level or on critical IP blocks
- Expert-level proficiency with Synopsys physical design tools: IC Compiler II, Fusion Compiler, PrimeTime, StarRC
- Proven experience leading design teams or managing complex physical design projects through tapeout
- Direct implementation experience in FinFET nodes at 16nm or below, ideally 7nm, 5nm, or 3nm
- Strong working knowledge of modern DFT concepts including scan, ATPG, and MBIST
- Familiarity with advanced packaging technologies, particularly flip-chip and multi-die integration
Who You Are:
- You can walk into a customer meeting with half-formed requirements and walk out with a technical plan that addresses the real constraints
- You push back when a customer request does not make physical sense, and you explain why in terms they will respect
- You think in project outcomes, not task completion. You know when to escalate, when to solve it yourself, and when to let the team figure it out
- Your design documents do not need three rounds of edits, and your technical presentations actually help people understand the problem
- You stay current with foundry roadmaps, EDA tool updates, and emerging standards because you know what worked at 7nm does not always work at 3nm
The Team You'll Be Part Of:
You will join the Engineering Project Management team within Synopsys Silicon IP, supporting the DDR, HBM, and UCIe PHY Hardening service line. This team works directly with customers and internal R&D to deliver production-ready IP implementations for the most advanced semiconductor projects in the world. You will collaborate with front-end design, physical design, verification, DFT, and ATPG engineers across global sites, and interface regularly with foundry partners and top-tier customers in AI, data center, and high-performance computing markets. The role is based in Taiwan.
