We Are:
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are:
You have spent years in the trenches of synthesis and place and route, working on designs where every picosecond and every microwatt matters. You know that the difference between winning a benchmark and losing it often comes down to how well you understand the silicon, the tools, and the customer's actual constraints, not just what the spec says. You have debugged enough timing violations and congestion hotspots to recognize patterns before they become problems, and you can walk into a customer meeting with a clear point of view on what will actually move their PPA numbers.
Working with R&D does not intimidate you. You speak their language, you understand what is possible versus what is a feature request that will take six months, and you know how to bridge that gap for customers who need answers now. You are comfortable presenting technical results to a room full of skeptical engineers who are evaluating your tools against three competitors, and you can do it in English with clarity and confidence.
At Synopsys, you will work on the most advanced CPU, GPU, and NPU designs in the industry, directly influencing both product direction and customer success.
What You'll Be Doing:
- Work directly with R&D teams to develop and refine advanced HPC reference flows for synthesis and physical design, feeding real customer use cases back into product development
- Run benchmarks on cutting-edge CPU, GPU, and NPU designs using DC, ICC2, and Fusion Compiler to demonstrate differentiated PPA results that win competitive evaluations
- Provide hands-on technical support to key global customers, diagnosing and resolving PPA bottlenecks in their most advanced designs at 3nm and below
- Deploy HPC methodologies and best practices to customers worldwide, translating complex flow optimizations into actionable guidance that accelerates their tape-out schedules
- Build and maintain automation scripts in Perl and Tcl to streamline benchmarking, flow deployment, and customer engagements
- Collaborate across time zones with engineering teams and customers in North America, Europe, and Asia to support critical design milestones and product launches
- Stay current with the latest advancements in ASIC design flow, advanced placement and routing rules, and CAD development to continuously improve the solutions you deliver
The Impact You Will Have:
- Your benchmark results will directly influence multimillion-dollar tool evaluations and win business with the world's leading semiconductor companies
- The reference flows you develop with R&D will be deployed globally, shaping how thousands of engineers approach synthesis and physical design on advanced nodes
- Your technical support will help customers achieve tape-out on schedule, preventing costly respins and accelerating time to market for next-generation AI and HPC chips
- The methodologies you deploy will improve PPA outcomes across customer designs, translating to measurable gains in performance, power, and area
- Your feedback loop with R&D will drive feature prioritization and product improvements that benefit the entire Synopsys customer base
- The relationships you build with key accounts will strengthen Synopsys' position as the trusted partner for the most challenging digital implementation problems
- Your work will contribute to the success of designs that power AI, data centers, and high-performance computing applications used by millions
What You'll Need:
- Bachelor's or Master's degree in Electrical Engineering or Computer Science with 4+ years of hands-on experience in synthesis or place and route
- Direct experience using EDA tools including Design Compiler, ICC2, and Fusion Compiler on real production designs
- Solid understanding of advanced placement and routing rules, timing closure techniques, and physical design optimization strategies
- Proficiency with scripting languages such as Perl and Tcl for automation and flow development
- Strong grasp of ASIC design flow, VLSI fundamentals, and CAD tool architecture
- Fluency in English, both written and verbal, sufficient to present technical content and engage in detailed customer discussions
- Experience with CPU, GPU, or NPU designs is a strong plus, particularly on advanced nodes at 5nm or below
Who You Are:
- You can walk into a customer meeting, listen to a complex PPA problem, and sketch out a viable solution path in real time without needing to escalate every question
- When a benchmark does not go as planned, you dig into the logs, identify the root cause, and iterate until the results tell the right story
- You are comfortable working across time zones and cultures, whether that means a late-night call with a team in California or an early morning session with a customer in Korea
- You do not wait for perfect information to move forward. You work with what you have, ask the right questions, and keep momentum going
- You have a never-give-up attitude when it comes to solving hard technical problems, and you are flexible enough to shift priorities when a critical customer engagement demands it
- You can explain a complex tradeoff between runtime and QoR to an engineering manager in two sentences without losing the technical nuance
The Team You'll Be Part Of:
Your recruiter will share more about the team structure and mission during the interview process.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
