職缺青蛙

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across cloud & AI, enterprise and carrier architectures, our innovative technology is enabling new possibilities. The package engineering team drives semiconductor IC package development from concept to mass production. The focus is New Product Introduction (NPI) which is a process that takes a concept of a semiconductor package solution and refines it into a final package design and product. There is the excitement of always working on new projects and cutting-edge technologies. What You Can Expect Understand the end product and/or end client requirements and define the optimal package solution for a given semiconductor product.  Working closely with cross functional teams – BU, CE, QA and Product engineering, define and provide package design inputs for manufacturability, supply, performance, cost, quality and reliability. Perform package design review. Manage and drive OSAT and substrate suppliers on risk assessment, design review and release, BOM and process, package char. and qual. Provide inputs to design guidelines and drive to implement the guidelines. Achieve milestone dates for all NPI schedules. Work with QA, OSAT/substrate suppliers to resolve package related quality/reliability issues. Provide inputs to the package technology roadmap. Support new package and technology development. What Were Looking For Bachelor’s degree in Mechanical Engineering and Material science or related fields and 5-7 years of professional experience in the semiconductor packaging field OR Master’s degree and/or PhD in ME and Material science or related fields and 3-5 years of professional experience in the semiconductor packaging field. Experience in substrate, RDL and assembly. Experienced with flip-chip package development and substrate review. Basic Cadence APD and AutoCAD skills. Understanding of semiconductor technologies, 1st-level assembly processes, semiconductor packaging materials, reliability standards and failure analysis techniques. The ideal candidate would be knowledgeable of 2D, 2.5D, 3D and wafer-level packaging. Good communication skills that can enable the candidate to work well with internal cross functional teams and suppliers. Good program management skills. OSAT management experience is a plus. Ability to work independently Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

• 職責：主導 Marvell 晶圓廠技術管理、云端優化矽晶片的晶圓廠工程與製造合作 • 領域：晶圓廠技術管理 / 半導體製造 • 技能：晶圓廠技術合作、製程技術管理、雲端基礎設施 IC、中央工程 • 亮點：Marvell Principal Technical Manager 職位，主導晶圓廠矽工程與雲端基礎設施 IC 製造合作

• 職責：設計開發評估維護量產測試設備及相關硬體、支援全球 OSAT 位置、散熱/機構測試操作 • 領域：散熱/機構測試作業 / 量產測試 • 技能：測試設備設計、散熱測試、機構測試、OSAT 支援、量產測試硬體 • 亮點：Marvell Senior Staff 測試作業工程師，支援全球製造測試硬體的設計開發與維護

• 職責：主導 APAC TSE 組 ATE 量產測試開發、技術卓越推動、跨地區協作 • 領域：測試解決方案工程 / APAC / ATE • 技能：ATE 測試開發、測試解決方案架構、量產測試優化、NPI 執行、技術領導 • 亮點：Marvell Senior Principal 工程師，在 APAC 新建 TSE 組的技術核心，主導高品質 ATE 測試開發

• 職責：建立領導 APAC TSE 團隊、ATE 量產測試開發、優化成本品質與 NPI 執行 • 領域：測試解決方案工程管理 / APAC • 技能：ATE 測試開發、測試解決方案、NPI 執行、團隊建立、APAC 地區管理 • 亮點：Director 職位，在 APAC 創建並領導 Marvell 全新 TSE 團隊，承擔量產測試開發的策略責任

• 職責：支援全球 ISO9001 品質管理系統、產品環境合規、RMA 流程、Six Sigma 推動 • 領域：品質管理系統 / ISO9001 • 技能：ISO9001、品質管理、RMA 流程、環境合規、Six Sigma • 亮點：Marvell 品質系統工程師學士實習，參與全球 ISO9001 品質管理系統實務

• 職責：驗證 Marvell 核心 IP 效能、提供業務部門與客戶技術支援、矽前後技術接觸 • 領域：應用工程 / SoC IP 驗證 • 技能：SoC IP 驗證、應用工程、矽技術支援、除錯 • 亮點：Marvell CE CSE 的碩士應用工程實習，驗證核心 IP 效能並為業務部門提供技術支援

• 職責：Marvell High-Speed SerDes IP 的硬體驗證實習、涵蓋 Switch/Automotive/Storage/Optics 多應用 • 領域：高速 SerDes 硬體驗證 / 類比 IC • 技能：SerDes 驗證、高速 IC 測試、類比量測、硬體驗證 • 亮點：Marvell Central Engineering HSS IP 的碩士硬體驗證實習，接觸業界最先進 SerDes IP 驗證

• 職責：為 Marvell 業務部門與客戶提供 IP 相關技術支援、矽前後技術接觸、除錯與支援 • 領域：應用工程 / SoC IP 支援 • 技能：SoC IP 支援、應用工程、矽技術接觸、除錯、客戶技術支援 • 亮點：Marvell CE CSE AE 的 Staff 應用工程師，為全業務部門核心 IP 提供矽前後技術支援

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact • Ability to operate both strategically and hands-on • Executive-level communication and judgment • Strong ownership mindset and reliability • Cultural fluency in working with global headquarters and local Taiwan teams What You Can Expect Country Manager & Executive Support Act as the primary support function for the Taiwan Country Manager, including coordination of priorities, meetings, and country-level initiatives Prepare executive-level materials related to events, customer engagements, and internal communications Serve as a trusted liaison between the Country Manager and corporate stakeholders Corporate Events & MarCom Plan and execute all Taiwan-based corporate events, including:CEO / executive all-hands meetings Team building activities Trade shows, industry events, and customer-facing programs Coordinate with global MarCom teams to ensure branding, messaging, and compliance with corporate guidelines Oversee event budgeting, vendors, agencies, and post-event reporting Visitor & Logistics Management Manage end-to-end logistics for foreign executives and visitors, including:Hotel bookings Transportation (limo service, site transfers) Event and meeting arrangements Ensure a high-quality, professional experience that reflects corporate standards and Taiwan business culture Cross-Functional & External Coordination Interface with internal teams (HR, Facilities, Finance, Global Marketing) to support country-level operations Manage external vendors, event agencies, and service providers Support additional country or corporate initiatives as assigned by the Country Manager What Were Looking For 10–15 years of professional experience, ideally combining:Marketing Communications (MarCom), Corporate Communications, or Event Management Executive assistant or chief-of-staff–type responsibilities Master’s degree preferred Background in IC design, semiconductor, or high-tech industry strongly preferred Proven experience supporting senior executives and managing high-visibility corporate events Fluent English communication skills (spoken and written); Mandarin required Strong organizational skills with the ability to manage multiple priorities independently Professional presence, discretion, and high attention to detail Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect IP/ASIC design verification engineer responsible for the verification and evaluation of digital circuits in high speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, test-case development and execution. He/She will be responsible for block and/or chip level verification and verification of PCIE, Ethernet, Serdes PHYs functions using UVM methodology, System Verilog What Were Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 7-8 years of related professional experience. Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-6 years of experience. Strong knowledge of UVM/OVM/VMM. Good knowledge of SystemVerilog/Verilog/C/C/System C. Solid background of random techniques, coverage-driven verification environment/flow. Strong ability of scripting languages such as Perl, Python, Makefile, C Shell. The ability to do Digital-Analog-Mixed simulations and develop UVM AMS models. Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent team Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Do you love building elegant solutions to highly complex challenges? Come to Marvell and be at the center of forefront Si foundry engineering and manufacturing for Marvell’s cloud-optimized Si in data infrastructure that keeps the world running. As a member of Foundry Technology organization under Central Engineering, you will have unrivaled opportunities to apply your talented skills on Si hardware yield management and ongoing support from productization standpoint that will impact Marvell’s swift response to the market. In this high-visibility position, you will work not only with Marvell’s Si foundry partners but also multiple Marvell functional teams to ensure successful launch of new products and mass production ramp of SOCs powering Marvell’s extraordinary product lines. What You Can Expect Work as a primary technical interface between foundry, Marvell teams (design, PE/TE, QA/Rel, supply chain and etc) and external customers for Tape out/NPI launch, yield, quality management Lead NPI to high volume and fast production ramp Able to detect any potential reliability risk and manufacturing weakness, positively identify the root cause and implement fixes before production Organize the efforts to accurately targeting the process to deliver the optimize product performance and production supply Responsibilities include device performance optimization, yield improvement, WAT analysis as well as process/Fab qualification. Ensure high production quality control by covering inline monitoring, SPC review, DPPM reduction, and root cause customer return defects Chance to engage in CPI(Chip Package Integration), CPO(Co-Package Optics) project, so the candidate with relevant experience is a plus. What Were Looking For MS degree and above in Engineering or Science (Electrical/Electronic Engineering, Physics, Electro-Physics, Material Engineering, etc) A minimum 10 years’ working experience in semiconductor technology development, fab process integration, product engineering, foundry management in IDM or foundry, fabless companies. Demonstrable expertise in Si manufacturing technology, yield enhancement, reliability, statistical process control, and failure analysis Team player, self-motivated and capable of working without supervision Keen engineering problem solving skills, execution-oriented mindset Excellent verbal and written communication, ability to interact effectively with operations staff, engineering peers in a result-oriented environment Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and/or chip level verification.The responsibilities include but not limited to.Improve the design methodology and flow. Design and verification for various types of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications. Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all the Marvell product lines. Provide the support to the product teams, for both pre and post silicon Test chip integration What Were Looking For * Master’s degree and/or PhD in EE, CS or related fields and 3 years of experience. * Good personal communication skills and team working spirit. * Hardworking and motivated to be part of a highly competent design team.Must be proficient in the following skills:Fundamental concepts in digital logic design Understand ASIC verification flows and methodologies Verilog and SystemVerilog/SystemC/Vera Strong Perl and Tcl scripting UNIX Shell scripting (Csh, Bash) ​ Highly desirable skills:Formal verification Low power design MATLAB and C/C based system simulation and evaluation DSP function hardware implementation knowledge Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. What You Can Expect ASIC design engineer responsible for post-RTL design flow. He/She will be responsible for block and/or chip level synthesis, timing closure, DFT generation, and ECOs. The responsibilities include but are not limited to. •    Improve the design methodology and flow. •    Synthesis, timing closure, and DFT support for various types of SerDes IPs ranging from 10Gbps to 224Gbps data rates for different applications. •    Collaborate with Analog/Digital design teams to deliver competitive SerDes IP solutions for all the Marvell product lines. •    Provide support to the product teams, for both pre and post-silicon What Were Looking For Master’s degree and/or PhD in EE, CS or related fields and 6 years of experience.   Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent design team. Must have good post-RTL experience including synthesis, timing analysis and physical design. Able to perform custom placement and routing for mixed-signal designs. Flexible to move between all post-RTL design activities as required. Good understanding of block and top-level physical timing closure. Must be proficient in the following skills: •    Logic or physical synthesis using Synopsys or Cadence tools •    DFT generation and verification •    Static timing analysis using Primetime •    Physical design for 28nm and beyond •    Strong Perl and Tcl scripting skill Highly desirable skills: •    Low power design •    Circuit level or custom design experience •    Floorplanning, clock-tree synthesis and power planning/analysis •    Signal integrity and physical verification Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a test development principal engineer in the Operations business group, you will test features on the silicon semiconductor chips Marvell produces for internal and external customers. You will make sure we don’t ship out any underperforming units. You’ll work closely with design to make sure their chip features are testable and that the results meet the customer’s specifications. You may even have to write new code or develop new testing strategies when our chips outpace the capabilities of current testing equipment. What You Can Expect Develop and optimize test methodologies for optical/electrical performance validation (e.g., IV, TIA/DRV behavior, MZM control, PD characterization). Design, set up, and maintain automated and semi-automated optical/electrical test stations. Cross-functional collaboration with design, packaging, and process teams to define test requirements and ensure design-for-test (DfT) alignment. Support test readiness for new product introduction (NPI) and mass production ramp. Interact with external vendors, contract manufacturers, and FA teams to resolve issues and improve test quality. Document test processes, procedures, and technical learnings in a structured, clear manner. What Were Looking For BS degree with 10yr or MS degree with 7yr in silicon photonics, optical and electrical device characterization and testing; Optics, EE, Physics or relevant major preferred. Hands-on experience with optical and electrical test equipment (SMU, Optical switch, OSA, tunable laser, polarization controller ..), tooling/jigs. Experience in equipment automation control for testing. Industry experience in Object-oriented scripting language like C, Python, Visual Basic, or LabVIEW for volume production highly preferred. Familiar with photonics concepts such as waveguides, modulators, photodetectors, tunable lasers, and fiber coupling techniques. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity  To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SYU

• 職責：資料中心 / AI 晶片數位 IC 設計、RTL 設計與驗證、跨功能團隊合作 • 領域：數位 IC 設計 / 資料中心 / AI 基礎設施 • 技能：RTL 設計、數位 IC、Verilog/SystemVerilog、資料中心晶片 • 亮點：Marvell 資料中心 AI 基礎設施關鍵 IC 設計職位，適合具備資深數位設計經驗的 Principal 工程師

• 職責：設計開發 SerDes PHY 及 AMS-IP 的類比 IC 電路、支援車用/儲存/安全/網路等多元應用 • 領域：類比 IC 設計 / SerDes / 多應用 • 技能：類比 IC 設計、SerDes PHY、混合信號、AMS-IP、高速傳輸 • 亮點：Marvell Central Engineering Sr. Staff 類比 IC 工程師，為所有業務部門的 SerDes PHY 及 AMS-IP 開發核心技術

• 職責：設計開發 SerDes PHY 及 AMS-IP 的類比 IC、為車用/儲存/安全/網路提供 IP 核心 • 領域：類比 IC 設計 / SerDes PHY / AMS-IP • 技能：類比 IC 設計、SerDes PHY、AMS-IP、高速類比電路、EDA 工具 • 亮點：Marvell Central Engineering Principal 類比 IC 設計工程師，為全公司提供 SerDes PHY 等核心類比 IP

• 職責：SerDes 電路設計、驗證與評估、高速資料通訊 IC 的類比混合信號 IP 開發 • 領域：類比 IC 設計 / SerDes / 高速通訊 • 技能：SerDes 電路設計、類比/混合信號、IC 設計驗證、高速通訊 IC • 亮點：Marvell Central Engineering AMS-IP 的碩士類比 IC 設計實習，參與 SerDes PHY 及 AMS-IP 開發

• 職責：伺服器與網路處理器光學封裝的產品工程、與 OSAT/廠商協作先進封裝技術開發 • 領域：光學封裝產品工程 / 數據中心 • 技能：光學封裝、伺服器/網路處理器、OSAT 管理、先進封裝、產品工程 • 亮點：Marvell Senior Staff 光學封裝產品工程師，投身最先進數據中心 IC 的光學封裝技術